1. Field of the Invention
The present invention relates to an apparatus for saving power consumption in semiconductor memory devices, and more particularly to a power consumption saving apparatus for semiconductor memory devices such as DRAM's, which is configured to preferentially latch a clock signal and a chip selection signal over other input command signals so that latch circuits for latching the input command signals are controlled in accordance with the clock signal and chip selection signal, thereby saving power consumption occurring in input latches not selected while reducing the size of output terminal drivers in a control chip. In particular, the present invention relates to a logic design for a semiconductor device, which is not only adapted to save unnecessary power consumption occurring in the semiconductor device when input command signals are entirely or partially input in sync with a certain signal such as a clock signal and controlled by a chip selection signal, but also adapted to reduce the output terminal driver size of a control chip.
2. Description of the Prior Art
Generally, system configurations using DRAM's include chips adapted to achieve desired control operations and chips adapted to be controlled by those control operations. The former chips are called "control chips" whereas the latter chips are called "DRAM's". An example of such system configurations is illustrated in FIG. 1. As shown in FIG. 1, the system may include a plurality of DRAM's controlled by a single control chip. In such a system, the control chip generates a plurality of command signals to be supplied to all DRAM's. The control chip also generates a chip selection signal to be supplied to a selected DRAM, in order to select the DRAM. In order to apply common signals to all DRAM's, it is required to use external signal paths corresponding in number to a value obtained by multiplying the number of DRAM's by the number of common signals to each DRAM. The common signals are output from the control chip along output lines, respectively. Selection of a desired one of the DRAM's to receive the common signals is determined by the chip selection signal. For example, where the control chip should send certain commands or addresses to a DRAM1, it is required to activate a chip selection signal associated with the DRAM1. Under this condition, external command signals are then applied to the activated DRAM1.
FIG. 2 illustrates the inner configuration of a conventional DRAM. As shown in FIG. 2, each command used in association with the DRAM synchronizes with a clock signal. The DRAM includes input pins to which a variety of signals are applied. At a stage following the input pins or terminals, input buffers are disposed which are coupled to the input pins, respectively. A plurality of input latches are disposed at the stage following the input buffers. Command signals applied to the input latches are synchronized with a clock signal in accordance with strobing operations of the input latches, respectively. The DRAM also includes a command decoder which receives the command signals from the input latches. In the command decoder, the command signals are decoded in accordance with a chip selection signal applied to the command decoder. After the decoding operation, the command decoder generates the resultant decoded signal as an internal command for the DRAM. Thus, command signals are applied to only a desired one of the DRAM's to which a chip selection signal is applied.
In such a system, however, the remaining DRAM's, other than the selected DRAM, are toggled in response to unnecessary command signals. As a result, power consumption increases greatly. Furthermore, this system has a problem in that the control chip thereof has an output stage driver size determined on the basis of not only the number of paths for external signals, but also the number of DRAM's.